See: Controller reading code Synchronized OAM Solutionīecause OAM DMA synchronizes the CPU and APU such that reads on an "even" CPU cycle never overlap a glitch, a program on an NTSC NES can miss all the glitches by triggering an OAM DMA as the last thing in vblank just before reading the controller, so long as all the reads are spaced an even number of cycles apart. This is not suitable for controllers that can't be reread, such as the Super NES Mouse. The standard solution used in most games using DMC will read the controller multiple times and compare the results to avoid this problem. Because it is not normally a compatibility issue, many emulators do not simulate this glitch at all. This detail is poorly represented in emulators. This glitch is fixed in the 2A07 CPU used in the PAL NES. On the standard controller this is most often seen as a right-press as a trailing 1 bit takes the place of the 8th bit of the report (right). Not correcting for this results in spurious presses. The program will see this as a bit deletion from the serial data. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge (a "double clock"), and the shift register will drop a bit out. If the DMC DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017, the values read will become invalid. Using DPCM sample playback while trying to read the controller can cause problems because of a bug in its hardware implementation. When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit. The CLK line for controller port is R/W nand (ADDRESS = $4016/$4017) (i.e., CLK is low only when reading $4016/$4017, since R/W high means read). The Four Score multiplayer adapter for NES only passes D0 from the connected controllers. The NES expansion port was never used commercially, but connects all 5 data lines to both ports. Some of the other lines can be connected through the expansion port on the Famicom. The Famicom hardwired controllers connect to D0, and $4016.D2 (microphone) only. The NES controller port makes only D0, D3 and D4 available for peripherals. NES standard controller, Famicom hardwired controller For the standard controller and Zapper which commonly came with the NES/Famicom: The specific use of each data line depends on the input device connected. The read value is inverted: a high signal from the data line will read as 0, and a low signal will read as 1.įor most devices it is necessary to read several times from these registers to collect multiple output bits from the device. $4016 reads only from controller port 1, and $4017 reads only from controller port 2. Reading from this register causes a clock pulse to be sent to the controller port CLK line on one controller, and one bit will be read from the connected input lines. Most other input devices operate in a similar way. Writing 0 to $4016 returns it to serial mode, waiting to be read out one bit at a time. Writing 1 to $4016 causes the register to fill its parallel inputs from the buttons currently held. On the standard controller this is connected to the parallel/serial control of a 4021 8-bit shift register. Its output will be continuously available on the OUT line of the controller port, and the expansion port. The low 3 bits written to this register will be latched and held.
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